1. Field of the Invention
The present invention relates to microcontrollers, and more particularly to a microcontroller having an improved access efficiency of an instruction with respect to a memory.
2. Description of the Related Art
The recent development of system LSI (Large-Scale Integration) has stimulated demand for memory-logic hybrid LSI devices. The enhanced performance of consumer products equipped with these LSI devices has necessitated increase in the speed of circuit and efficiency of execution of a program.
FIG. 6 is a block diagram of a structure of a conventional microcontroller. A description will be given of an exemplary case where a flash memory is used as a memory built in the microcontroller.
The conventional structure of the microcontroller is equipped with a CPU (Central Processing Unit) 101, which is connected to a bus control unit 102 through an instruction bus Ibus used exclusively for instructions and a data bus Dbus used exclusively for data, these buses being provided independently. The bus control unit 102 is connected to a flash interface circuit 103 through a flash memory bus Fbus. A flash memory 104 is connected to the flash interface circuit 103. An instruction cache memory 105 used to improve the efficiency of execution of instructions is connected to the instruction bus Ibus interposed between the CPU 101 and the bus control unit 102. A control line 106 used to transfer a cache control signal is connected to the CPU 101, the bus control unit 102 and the instruction cache memory 105.
The flash memory 104 is subjected to both the instruction access and the data access, and is thus connected to the flash memory bus Fbus, which is provided separately from the instruction bus Ibus and the data bus Dbus and is called a Princeton bus.
A description will be given, with reference to FIG. 7, of an operation of the microcontroller configured as described above.
FIG. 7 is a timing chart of an instruction access operation of the microcontroller. More particularly, FIG. 7 shows a clock signal, an instruction bus address IA, instruction bus data ID, a flash memory bus address FA, flash memory bus data FD, and a cache miss decision signal, which are illustrated in that order from the top of FIG. 7.
An instruction access from the CPU 101 to the flash memory 104 is performed as follows. First, the CPU 101 outputs the instruction bus address IA to the instruction bus Ibus. When the cache hit occurs, in other words, when instruction bus data ID corresponding to the instruction bus address IA is available in the instruction cache memory 105, the flash memory 104 immediately responds to the instruction bus address IA. Thus, the cache-hit instruction bus data ID can be read from the instruction cache memory 105 in one cycle.
If the requested instruction bus data does not remain in the instruction cache memory 105, the CPU 101 must have access to the flash memory 104 again. At the time of accessing the instruction cache memory 105, a decision cycle is required to make a decision as to whether the requested instruction bus data is available in the instruction cache memory 105. When the cache miss occurs in the decision cycle, the cache miss decision signal is sent to the bus control unit 102 over the control line 106 in the second cycle. The bus control unit 102 acknowledges the cache miss decision signal, and outputs the flash memory bus address FA to the flash memory bus Fbus in the third cycle. That is, the bus control unit 102 acquires the instruction bus address IA in the second cycle, and outputs the flash memory address FA in the third cycle. Therefore, the outputting is delayed by one cycle, and the second cycle serves as a penalty cycle. The flash interface circuit 103 accesses the flash memory 104 in the fourth cycle, from which the flash memory bus data, which is cache-missed data, is read out to the flash memory bus Fbus. The flash memory bus data FD thus read is the instruction bus data ID. As described above, it takes four cycles for the requested instruction bus data ID to become available when the cache miss occurs, while it takes only one cycle when the cache hit occurs.
In a comparative structure in which the instruction cache memory is not employed, the flash memory 104 is accessed for each instruction access. In addition, since the penalty cycle is not required, it is enough to have three cycles to complete the instruction access. More particularly, as shown in FIG. 8, the instruction bus address IA is output in the first cycle, and the flash memory bus data FD specified by the flash memory bus address FA is acquired in the second cycle. In the third cycle, the flash memory bus data FD is acquired as the instruction bus data ID.
As described above, the bus control unit 102 needs the control time of two cycles in order to realize the high-speed circuit operation when the instruction access from the CPU 101 to the flash memory 104 is performed. Thus, it surely takes at least three cycles to complete the instruction access in the case where the instruction cache memory 105 is not employed. In contrast, in the case where the instruction cache memory 105 is employed in such a way as to be connected to the instruction bus Ibus in order to improve the efficiency of execution of instructions, it is possible to complete the instruction access in only one cycle when the cache hit occurs. However, the penalty cycle is added when a cache miss occurs, and thus it takes four cycles to complete the instruction access. In other words, the number of cycles at the time of the occurrence of a cache miss is one cycle larger than that it takes in the absence of the instruction cache memory 105. It may be conceivable to increase the capacity of the instruction cache memory 105 in order to improve the cache-hit rate. However, this needs a larger chip area and the cost of the microcontroller becomes higher.
As a method for having access to the flash memory access in only one cycle, a circuit configuration is known in which the flash memory is connected to the instruction bus. Such a configuration is shown in FIG. 9, which illustrates another conventional structure of the microcontroller.
The microcontroller shown in FIG. 9 has the instruction bus Ibus to which the flash interference circuit 103 and the flash memory 104 are connected in such a way as to be closer to the CPU 101 than that shown in FIG. 6. With the above arrangement, the CPU 101 can access the flash memory 104 without the bus control unit 102, so that a one-cycle data access can be performed.
However, the arrangement with the flash memory connected to the instruction bus requires a modification of the bus protocol so as to make it possible to perform not only the instruction access to the flash memory but also the data access thereto. This is because the instruction bus is originally provided for instruction access only. In addition, the above arrangement requires a modification of the bus control unit, which makes the control thereof complex.
Furthermore, the above-mentioned arrangement loses the advantage of the high-speed circuit operation resulting from the separate arrangement of the instruction bus and the data bus. This is because the CPU cannot read any instruction during data access, and thus cannot perform instruction access.
Taking the above into consideration, an object of the present invention is to provide a microcontroller which has a structure installable in a conventional circuit configuration including a cache memory without any modification thereof and allows a central processing unit to have memory access in only one cycle.
To accomplish the above object, according to the present invention, there is provided a microcontroller having an instruction cache control function including: a central processing unit; a bus control unit connected to the central processing unit through an instruction bus and a data bus provided independently; a memory interface circuit receiving the instruction bus and a memory bus extending from the bus control unit and controlling an instruction access via the instruction bus and a data access via the memory bus; and a memory subjected to the instruction access and the data access via the memory interface circuit.